Integrated circuits made with SOI technology have a certain number of advantages. Such circuits generally show lower static and dynamic electricity consumption for equivalent performance, owing to an improved electrostatic control of the channel by the gate. Because there is a non-doped channel, the dispersions of the electrical characteristics are also smaller. Such circuits generally result in lower parasitic capacitances, thus improving switching speed. Furthermore, the latch-up or parasitic triggering phenomenon encountered by MOS transistors in bulk technology can be avoided to the benefit of operating robustness, owing to the presence of the insulating oxide layer. Such circuits therefore prove to be particularly suited to SoC type applications. It is generally noted that SOI integrated circuits are less sensitive to the effects of ionizing radiation and hence prove to be more reliable in applications where such radiation can give rise to operational problems, especially in space applications. SOI integrated circuits can especially include SRAM random-access memories or logic gates. The making of SOI integrated circuits also remains relatively similar to that of bulk technology.
Reducing the static consumption of logic gates while at the same time increasing their switchover speed has been the subject of much research. Certain integrated circuits being developed integrate both low-consumption logic gates and high-switchover-speed logic gates. To generate both these types of logic gates on a same integrated circuit, fast-access logic gates or low-consumption logic gates are chosen from libraries of logic gates. In bulk technology, the threshold voltage level of transistors of a same type is modulated by differentiating their channel doping level. However, in FDSOI (Fully Depleted Silicon-On-Insulator) technology, the doping of the channel is almost zero. Thus, the channel doping level in the transistors cannot show major variations without losing the associated advantages, and this fact makes it impossible to differentiate the threshold voltages by bringing this doping into play. The threshold voltages in non-doped channel FDSOI technology are thus essentially determined by the work function of the gate. A work function slightly below the midgap, known as an N-type work function, for NMOS transistors is generally desired to obtain threshold voltages between 0.2 and 0.5V. Symmetrically, a work function slightly above the midgap, called a P-type work function, for PMOS transistors is generally desired to obtain threshold voltages between −0.2 and −0.5V.
In order to have distinct threshold voltages for different FDSOI technology transistors, there are also known ways of using a biased ground plane placed between an insulating thin-oxide layer and the silicon substrate. By playing on the doping of the ground planes and on their biasing, it is possible to define a range of threshold voltages for the different transistors. We could thus have low-voltage-threshold or LVT transistors, high-voltage-threshold or HVT transistors and medium or standard-voltage-threshold or SVT transistors.
The transistors of an integrated circuit are generally laid out in dual alternating rows of NMOS and PMOS transistors. A row of NMOS transistors is separated from a row of PMOS transistors by an insulation trench. In order to have transistors with different voltage thresholds in a same row, certain transistors are laid out so as to be plumb with an N-type doped ground plane while the other transistors are laid out to be plumb with a P-type doped ground plane.
The US document US2003/178622 (D1) describes an integrated circuit comprising a stacking of a semiconducting substrate, a buried insulating layer and a semiconducting layer. A transistor is formed in and on said semiconducting layer. A bias circuit is configured to generate a first bias voltage. A first via-type interconnection receives the first bias voltage. A first insulation trench separates the transistor from the first interconnection and from a second interconnection in the semiconducting layer. A first well has P-type doping, is placed beneath the buried insulating layer plumb with the transistor and extends beneath the first insulation trench until it makes contact with the first interconnection. A second well has N-type doping and is placed so as to be plumb with the first well and extends beneath the first insulation trench until it makes contact with the second interconnection. The biasing of the first well is variable to modulate the threshold voltage of the transistor. The second well insulates the first well from a P-doped substrate and has a bias greater than that of the first well in order to limit leakages.
It is observed, on the one hand, that the time of diffusion of the bias within a ground plane is relatively long and, on the other hand, that a relatively complex design is needed for the circuit in order to prevent the formation of conductive parasitic diodes between the different doping levels of the semiconductors as a function of the bias that is applied to them. Besides, the formation of contacts with a view to biasing the different types of ground planes proves to be complex and implies the use of a considerable surface area of transition cells to the detriment of integration density.